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| Semiconductor September 1997 EW RN D FO 81 DE 8 MEN SP43 COM See H RE NOT IG DES NS HSP43481 Digital Filter Features * Four Filter Cells * 0MHz to 30MHz Sample Rate * 8-Bit Coefficients and Signal Data * 26-Bit Accumulator per Stage * Filter Lengths Up to 1032 Tap * Expandable Coefficient Size, Data Size and Filter Length * Decimation by 2, 3 or 4 Description The HSP43481 is a video-speed Digital Filter (DF) designed to efficiently implement vector operations such as FIR digital filters. It is comprised of four filter cells cascaded internally and a shift-and-add output stage, all in a single integrated circuit. Each filter cell contains an 8 x 8 multiplier, three decimation registers and a 26-bit accumulator which can add the contents of any filter cell accumulator to the output stage accumulator shifted right by eight-bits. The HSP43481 has a maximum sample rate of 30MHz. The effective multiplyaccumulate (MAC) rate is 120MHz. The HSP43481 can be configured to process expanded coefficient and word sizes. Multiple devices can be cascaded for larger filter lengths without degrading the sample rate or a single device can process larger filter lengths at less than 30MHz with multiple passes. The architecture permits processing filter lengths of over 1000 taps with the guarantee of no overflows. In practice, most filter coefficients are less than 1.0, making even larger filter lengths possible. The HSP43481 provides for unsigned or two's complement arithmetic, independently selectable for coefficients and signal data. Each DF filter cell contains three resampling or decimation registers which permit output sample rate reduction at rates of 1/ , 1/ or 1/ the input sample rate. These registers also pro2 3 4 vide the capability to perform 2-D operations such as N x N spatial correlations/convolutions for image processing applications. Applications * 1-D and 2-D FIR Filters * Radar/Sonar * Adaptive Filters * Echo Cancellation * Complex Multiply-Add * Sample Rate Converters Ordering Information PART NUMBER HSP43481JC-20 HSP43481JC-25 HSP43481JC-30 HSP43481GC-20 HSP43481GC-25 HSP43481GC-30 TEMPERATURE RANGE 0oC to +70oC 0oC to +70oC 0oC to +70oC 0oC 0oC to +70oC +70oC 0oC to +70oC to PACKAGE 68 Lead PLCC 68 Lead PLCC 68 Lead PLCC 68 Lead PGA 68 Lead PGA 68 Lead PGA Block Diagram VCC DIENB CIENB DCM0 - DCM1 ERASE TCCI CIN0 - CIN7 RESET CLK ADR0 - 1 8 4 VSS DIN0 - DIN7 TCS 8 5 8 FILTER CELL 0 4 2 MUX RESET CLK SHADD SENBL SENBH 2 ADR0, ADR1 2 26 OUTPUT STAGE 26 8 8 FILTER CELL 1 26 8 8 FILTER CELL 2 26 8 8 FILTER CELL 3 26 TCCO 8 COUT0 - COUT 7 COENB SUM0 - 25 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) Harris Corporation 1997 File Number 2759.4 3-1 DB302 26 |
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